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<@U02AZBZ4AH0> Doesn't `make user_project_wrapper`...
# shuttle
m
@User Doesn't 
make user_project_wrapper
give you this?
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[ERROR]: instance mprj port wb_eno not found in /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
[ERROR]: instance mprj port wb_gs not found in /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
[ERROR]: Check whether EXTRA_LEFS is set appropriately and if they have the referenced pins.
m
No because i have instatiated 'wb_eno' as 'io_out' and 'wb_eno' was enable signal that i have used in user_proj_example 🙂
Does that create any problem ?? 🙂
m
@User When I try to synthesize your design, it stops at the error message above. I don't have that much experience, so I can't give you advice.
j
@User can you please comment on the above
m
@User your lef doesn't have those ports
how did you harden your design? after make user_proj_example suceeds it should copy the gds, lef etc to the correct directories
m
Yes after <make user_proj_example> gds lef def and each were copied to there respective directories by default
In beginning i used wb_eno then I replaced them with eno and similarly some pins
But Please help me to find the solution to overcome Klayout Beol check as It's showing 6 drc error
m
@User You can load the marker file into klayout to see where the DRC errors are. In klayout, choose 
Tools -> Marker Browser
and then load 
precheck_results/<timestamp>/outputs/reports/klayout_beol_check.xml
If you need help understanding specific DRC errors, please post the DRC error message.
m
how to fix these any suggestions please 🙂
m
Looks like your 
via4
spacing < 0.8um. You can see the rule here: https://skywater-pdk.readthedocs.io/en/latest/rules/periphery.html#via4
Here's the screenshot. Don't know why the power router does this. I've seen it in other designs too.
m
@User very cool to link it to the rules. That would be a great addition to DRC error messages, automatic linking to the relevant section in the rules.
m
@User, @User thanks for going through the design, what should I do now, any command that will help to overcome this error, or I had to do it manually 🙃
m
@User I think it may be a setting problem. I'm asking now in #openlane
m
okay thanks @User
m
@User How did you create the GDS file for 
user_project_wrapper
?
m
I used command make user_project_wrapper Which created all the layouts and netlists 🙂
Just as it was mentioned in Documentation of caravel user project
m
When I do that, I get
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[ERROR]: instance mprj port wb_eno not found in /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
[ERROR]: instance mprj port wb_gs not found in /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
[ERROR]: Check whether EXTRA_LEFS is set appropriately and if they have the referenced pins.
How did you fix this?
m
I think that's because first i run make user_proj_example Which have all the ports that i have instantiated in verilog netlist of wrapper 🙂
Here are the snaps of what I mean to say 🙂
m
I'll try that.
@User This is the thread concerning the via4 spacing after routing. Using openlane tag 
mpw-3a
from 
<https://github.com/efabless/OpenLane.git>
, I've verified that the following steps give the same error.
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git clone <https://github.com/Khalique13/caravel_vsd_priority_encoder>
cd caravel_vsd_priority_encoder
make install
make user_proj_example
make user_project_wrapper
make precheck
make run-precheck
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