Hi all, My design only uses LA ports to connect to the user space logic. However there’s a statement in efabless website that says:

Checklist for Open-MPW Submission
...
✔️ Full Chip Simulation passes for RTL and GL (gate-level)
...

So do I need to pass every test in the

dv

folder, or is it possible to write my custom test based on the way I use the LA ports? @User @User @User

you need your own tests. The tests in the dv folder are only for the example project. They will probably all fail with your custom project

@User That’s exactly correct Matt. So may I get rid of all the other tests and only provide one (my own custom test)?

yes

Thanks Matt.