When I run the user_project_wrapper, I see error message during synthesis. "ERROR: Unimplemented compiler directive or undefined macro `MPRJ_IO_PADS". Also, attached is the 1-synthesis.log file. Please help.

It means it's not defined in verilog. My assumption is that the defines.v is not included or is not in configured to be in verilog source list.

$::env(CARAVEL_ROOT)/verilog/rtl/defines.v need to be set. Refer https://github.com/efabless/caravel_user_project/blob/main/openlane/user_project_wrapper/config.tcl

Thanks, It works!