Has anybody tried to write to the io_pads > 31? i.e using

reg_mprj_datah

? I think it is not working for me. Upon looking the waveform, pin 32 never gets high when I set it like

reg_mprj_datah = 0x00000001

Need a bit more information. . . Is this happening in RTL verilog simulation on the current version of caravel? There are a number of testbenches for caravel that exercise the upper I/O pins; these testbenches have to pass RTL and GL simulation as part of our CI for caravel. See, for example,

caravel/dv/caravel/mgmt_soc/timer/timer.c

, which uses GPIO 32 to 37 to signal to the testbench verilog the part of the code that is being exercised.

Okay, I think for me io_pin 32 and 33 were not working. But I changed to 34 to make it work. I will take time out for this to see what actually was the problem.

did you get it figured out @User?

No pretty caught up with studies rn. I'll look at it after March 16th

I checked for you

Thanks! I wonder why they didn't for me? I'll look more closely after being done with the quarter.

Output enable or not setup in firmware would be my guess