Hello, I have hardened my design using Cadence-Innovus. I am currently facing the issue of pin overlap. If I open the my design in klayout I see the IOs have 

pin layer

 but they are not enclosed by the 

drawing layer

 . However, I only see the met2 layer for IO placement in Cadence. There isn't any 

met2 pin layer

 or 

met2 drawing layer

we were having this problem as well, it's from the layer map file you use in Innovus to export the layout to GDS. we ended up writing our own here: https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/extra/sky130_lefpin.map

@User Thanks alot