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When I extract from one of the standard cells, it does it inside a subckt. If I extract something I've drawn by hand, it isn't enclosed in a subckt. What's the difference between them? And how do I make my own cells get extracted the same?

I think it depends on whether you have ports defined or not

There is an option:
ext2spice subcircuit top on

This will enclose a hand draw circuit in a subcircuit.

Or, you can specify in your LVS script that one is in a subcircuit and one is not.