I’m trying to extract spice from a def I got from cadence innovus, and magic is not figuring out that the vnb should be tied to vss (it instead ties all vnb to a common node that is not vss) and that the vpb should be tied to vdd (it seems to tie the vpb’s of each std cell row to a common node). Any idea what’s going on?

is the common node

VSUB

by any chance? And are does the design include tap cells?

Yes the common node for vnb is VSUBS

ok, you may need to get Magic to flatten the hierarchy before performing extraction, @Tim Edwards told me about a problem which currently exists which was something along the lines of connectivity of certain layers not propagating through up through the hierarchy IIRC. This is my LVS script for reference.

Awesome thanks

It's always best to start with something simple I think. E.g. draw a schematic with one inverter, and then create a layout with one inverter and a vpwr vgnd tap cell. Then extract and run lvs

Yeah the issue was that I wasn’t inserting tap cells. Thanks Tom for the help.

Pleasure. Glad you got it working

@James Thomas: You should not need to flatten the circuit before doing LVS unless you are doing something like putting a deep nwell under the standard cell design.