@User Do you plan to add checking for the low tap density layer in a future revision, and check for higher tap density in it's absence?

Not really. To me, and other people I've talked to, the "normal" tap density seems like incredible overkill. I have a hard time believing that the higher tap density is really needed. Regardless, for the Caravel chip, the user area does not come closer than 50um to the padframe, so the higher tap density is not required anywhere.

@Tim Edwards ah interesting, so is the increased requirement when close to the pad frame due to the increased currents and transients resulting from the IO structures then?