@User, is there a specific string I can look for in the netgen report to determine whether LVS has passed or not? I noticed that it can say that the circuits match uniquely and then later report property errors etc. so I want to know what you recomend as a reliable fool proof "PASS" indicator. Cheers!

The official pass/fail is to include the "-json" switch on the "lvs" command, and then run the output JSON file through the script "count_lvs.py" which is part of qflow. From the text output, the "match uniquely" line indicates the cell is topologically correct. A line with "property errors" or "failed pin matching" is a mismatch you may or may not care about depending on the circumstances. If you force subcircuits to be declared matching, then you can get one additional line with "subcells failed to match". Those are the only three lines that would indicate something wrong or needs attention after declaring a topological match.

Thanks, @Tim Edwards