Hello all, I am facing some difficulties in creati...
# magicv
Vinodhini G Edward
10/08/2021, 5:48 PMHello all, I am facing some difficulties in creating a multi finger transistor in magic with parallel connection by overlapping the diffusion area. I could realize a parallel connections of two transistors by placing them individually and by connecting the source with source, drain with drain and gate with gate. By default left side diffusion area is assigned as source and right side as drain, When i try to overlap the drain diffusion area and merge two of the drain terminals together by flipping one of the transistors, I couldn't succeed in generating the overlap (SD-DS) . When i generate the spice netlist , I could see the transistors are only in series connection(SD-SD). Is there any way to realize parallel connections of transistors by overlapping the diffusion area?
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Tim Edwards
10/08/2021, 5:57 PM@Vinodhini G Edward: The extraction can't differentiate between source and drain, since they're symmetrical. You can "stamp" the source and drain regions with the text label "D$" or "S$" to force the extractor to treat them as intended. The labels must be zero-area labels attached to the boundary between the gate and the source or drain. Generally, though, it makes no difference to simulation or LVS which end is which.
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Arman Avetisyan
10/08/2021, 6:12 PM... unless he is accidently not providing .tcl file to netgen. Which was my mistake, apparently if no .tcl files is found in the path netgen continues in blackbox mode.
Arman Avetisyan
10/08/2021, 6:13 PMthis means that netgen will think that D/S are not symmetrical
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Vinodhini G Edward
10/08/2021, 6:14 PM@Tim Edwards. Thanks you for the response. will try this out
Vinodhini G Edward
10/08/2021, 6:17 PM@Arman Avetisyan Hi,thanks for the response. Do you mean to include .tcl file while running LVS?
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Tim Edwards
10/08/2021, 7:08 PM@Vinodhini G Edward: Yes. Netgen must be invoked as something like
netgen -batch lvs "file1 cell1" "file2 cell2" sky130A_setup.tcl comp.outsky130A_setup.tclv
Vinodhini G Edward
10/09/2021, 9:29 AM@Tim Edwards okay, thanks a lot.
Vinodhini G Edward
10/10/2021, 5:05 PM@Tim Edwards I am trying to realize a transistor with multiplier 4. When I place the transistors in a single column, and connect all the sources , drains and gate together, I do not get any lvs errors, compared to the xschem file for a single transistor with a multiplier of 4. (I am using the above command to run lvs), However, when i try to place it as a square (2*2) and do the parallel connection, i get an error in the lvs, saying the circuits do not match and my circuit contains 2 devices. Is there a way to overcome this?
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Tim Edwards
10/10/2021, 8:42 PM@Vinodhini G Edward: I'm not at all sure why there would be a difference in the extracted netlist between the 4 columns and the 2x2 array. Can you share the example?
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Vinodhini G Edward
10/11/2021, 3:24 AM@Tim Edwards. I had actually tried out for an multiplier of 8 (1*8: file name- nmos5518) and(2*4:file name- nmos 5524 ). Attaching the mag file, extracted netlist extracted spice netlist for both and the xschem_file (file name-test.spice).
Vinodhini G Edward
10/11/2021, 3:27 AM@Tim Edwards The spice net list of nmos5514 matches with test.spice, whereas nmos5524 doesn't match.
Vinodhini G Edward
10/11/2021, 2:36 PM@Tim Edwards I just understood the mistake that i made, by comparing the spice net list including the extracted parasitic capacitances! Thank you for taking your time
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