@User Hi Tim, I’m creating a DRAM cell for fun. Here is the output of the Magic for the attached layout:

* NGSPICE file created from DRAM.ext - technology: sky130A

.subckt sky130_fd_pr__nfet_01v8_EDB9KC a_n33_n130# a_15_n42# a_n73_n42# w_n211_n252#
X0 a_15_n42# a_n33_n130# a_n73_n42# w_n211_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
C0 a_n73_n42# a_n33_n130# 0.03fF
C1 a_15_n42# a_n73_n42# 0.15fF
C2 a_15_n42# a_n33_n130# 0.03fF
C3 a_15_n42# w_n211_n252# 0.10fF
C4 a_n73_n42# w_n211_n252# 0.10fF
C5 a_n33_n130# w_n211_n252# 0.31fF
.ends

.subckt sky130_fd_pr__cap_mim_m3_1_FJFAMM c1_n250_n200# m3_n350_n300# VSUBS
X0 c1_n250_n200# m3_n350_n300# sky130_fd_pr__cap_mim_m3_1 l=2e+06u w=2e+06u
C0 c1_n250_n200# m3_n350_n300# 0.83fF
C1 m3_n350_n300# VSUBS 0.66fF
.ends

.subckt DRAM GND WL BL TEST
Xsky130_fd_pr__nfet_01v8_EDB9KC_0 WL m1_346_386# BL GND sky130_fd_pr__nfet_01v8_EDB9KC
Xsky130_fd_pr__cap_mim_m3_1_FJFAMM_0 TEST GND GND sky130_fd_pr__cap_mim_m3_1_FJFAMM
C0 TEST m1_346_386# 0.27fF
C1 WL TEST 0.04fF
C2 WL m1_346_386# 0.06fF
C3 BL m1_346_386# 0.03fF
C4 BL WL 0.37fF
C5 WL GND 0.96fF
C6 TEST GND 0.23fF
C7 m1_346_386# GND 0.15fF
C8 BL GND 0.83fF
.ends

As you can see in the extraction process there are two different signals named

m1_346_386#

and

TEST

. However these two signals are the same (as you can see in the layout). The result of the extraction leads to some

ngspice

issues and unsolvable circuit. Is it a kind of bug?

From the output, it appears that "TEST" does not make a contact to the transistor. Is the entire contact stack there?

@User I’m so sorry for the inconvenience. You were 100 percent right. I forgot the

via2

.