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<@U016EM8L91B> <@U017X0NM2E7> I have a simple desi...
# magic
m
@User @User I have a simple design using sky130_fd_sc_hd standard cells and if I extract it in magic 8.3.245, it doesn't extract the VNB and VPB ports, but if I extracted it in 8.3.197, it does. Any idea what changed? I'm doing a: readspice foo.spc extract ext2spice Where foo.spc has connections on VNB and VPB pins to supplies. The design also passes LVS and when I extract with ext2spice lvs, it includes the VNB and VPB ports. Edit: Using readspice seems to remove the VNB and VPB ports... so if I extract without it, they are present. However, then the port order could be different.
t
Try version 8.3.270, since I fixed one thing in the extraction code that is known to cause issues with the VNB port. Still, nothing should affect the VPB port. Sounds more like the long-ago problem with the old LEF views not having nwell and pwell defined. Okay, I re-read your post and realized that you meant that the problem was being caused by readspice. This seems odd because I use readspice as part of the open_pdks installation, and there it properly annotates all of the standard cells. Can you post the example?
m
This test does it -- it's a simple 5 stage inverter circuit called TEST.
test.tar.gz
Extracted with the older version:
Copy code
* SPICE3 file created from TEST.ext - technology: sky130A

.subckt TEST IN OUT VPWR VGND
Xsky130_fd_sc_hd__inv_1_4 sky130_fd_sc_hd__inv_1_5/Y VGND VGND VPWR VPWR sky130_fd_sc_hd__inv_1_4/Y
+ sky130_fd_sc_hd__inv_1
Xsky130_fd_sc_hd__inv_1_5 IN VGND VGND VPWR VPWR sky130_fd_sc_hd__inv_1_5/Y sky130_fd_sc_hd__inv_1
Xsky130_fd_sc_hd__inv_1_0 sky130_fd_sc_hd__inv_1_4/Y VGND VGND VPWR VPWR sky130_fd_sc_hd__inv_1_1/A
+ sky130_fd_sc_hd__inv_1
Xsky130_fd_sc_hd__inv_1_1 sky130_fd_sc_hd__inv_1_1/A VGND VGND VPWR VPWR sky130_fd_sc_hd__inv_1_2/A
+ sky130_fd_sc_hd__inv_1
Xsky130_fd_sc_hd__inv_1_2 sky130_fd_sc_hd__inv_1_2/A VGND VGND VPWR VPWR OUT sky130_fd_sc_hd__inv_1
C0 VPWR VGND 2.55fF
.ends
Extracted with the newer version:
Copy code
* SPICE3 file created from TEST.ext - technology: sky130A

.subckt TEST IN OUT VPWR VGND
Xsky130_fd_sc_hd__inv_1_4 sky130_fd_sc_hd__inv_1_5/Y VGND VPWR sky130_fd_sc_hd__inv_1_4/Y
+ sky130_fd_sc_hd__inv_1
Xsky130_fd_sc_hd__inv_1_5 IN VGND VPWR sky130_fd_sc_hd__inv_1_5/Y sky130_fd_sc_hd__inv_1
Xsky130_fd_sc_hd__inv_1_1 sky130_fd_sc_hd__inv_1_1/A VGND VPWR sky130_fd_sc_hd__inv_1_2/A
+ sky130_fd_sc_hd__inv_1
Xsky130_fd_sc_hd__inv_1_0 sky130_fd_sc_hd__inv_1_4/Y VGND VPWR sky130_fd_sc_hd__inv_1_1/A
+ sky130_fd_sc_hd__inv_1
Xsky130_fd_sc_hd__inv_1_2 sky130_fd_sc_hd__inv_1_2/A VGND VPWR OUT sky130_fd_sc_hd__inv_1
.ends
Now that I think about it, it seems like this is something to do with the changing definition and merging of ports...
Commands used: readspice TEST.spc extract ext2spice
Actually, this does not extract the VNB and VPB even without the readspice...
One workaround is to ext2spice hierarchy on which extracts the standard cells too
t
What's wrong here is that with "ext2spice hierarchy off", it is not flattening it down to the transistor level. It is stopping at the inverter cells, and since the top level connects the well and substrate, those ports are eliminated. But you can't see that because it has not output the definition of the inverter. Apparently I broke the code where it flattens the circuit, probably a trivial error.
m
ok, so the fix can just be to add the hierarchy for us. This is my class project in sky130 🙂
(Not the small design, but using sky130 stuff...)
t
Looks like what happened is that I have an option "ext2spice subcircuit on" that causes flattening to stop at standard cells and outputs the standard cells instead of descending into them and outputting transistors. The recent code changes that affect the way ports are generated and written out are not paying attention to the "subcircuit on" setting and so are making unwarranted optimizations in the ports. So it's a bit less trivial than I thought. If you have a workaround, then I'm going to post an issue in the issue tracker and then punt on it until I've worked through some other critical items on my to-do list.
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