<@U016MJQ06J2> Since that time, we split the data ...
# openramm
Matthew Guthaus
09/11/2020, 7:00 PM@User Since that time, we split the data bus into a separate input and output bus for more flexibility. That is the only option now.
a
ALI AHMED
09/12/2020, 5:06 PMThanks
ALI AHMED
09/13/2020, 4:27 AMAnother question, just to verify : We are going to use this verilog file: https://github.com/VLSIDA/OpenRAM/blob/ed9d32c7bc105db2a438d36d4b2d852152a79e3b/compiler/tests/golden/sram_2_16_1_freepdk45.v
Is it the same SRAM IP generated by the Compiler for Skywater 130 nm?
m
Matthew Guthaus
09/13/2020, 3:25 PMYes, that will be representative behaviorally.