Hi Can we access a memory column wise? I have 32-bits word align memory and I want to to access second byte to write something on that in one cycle...

Yes, it supports write masking which let's you write a fixed but configurable subset of bits.

thanks

@Matthew Guthaus In a maskable write, is it disabling of WBL and WBL(bar) for specific set of SRAM cells in selected row of Memory array as interface for writing in a cell, as din (data in ) bits are fixed at interface, for e.g. 32 X 32 SRAM has 32 bits din , but i want to write only last byte (8 lsbs from 32 bits of din) so i should provide a WBM (write bit mask) signal at interface of 4 bits , which is 1110 in this case, here 0 means actual write and 1 means mask? So first 24 bits (WBL and WBL(bar)) will be deactivated, so there is no writing in those SRAM cells despite of any data change at din (data in), and only last 8 bits will be affected. Am i correct in assumption or there is something else inside?

Yes, that is basically correct.

Thanks, it is a good read, please if you can share a github repository link for the implementation of Pico SoC using Open RAM memories?

I don't have it accessible since I am on vacation this week

no issue, thanks @Matthew Guthaus.

OpenRAM cannot handle 3 ports yet. This is on the future list though.

Thanks @Matthew Guthaus, @Zeeshan Rafique please check.

Thanks @ALI AHMED , @Matthew Guthaus