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I have read in another thread that ROM functionali...
# openram
j
I have read in another thread that ROM functionality is to be added at some point to openRAM. Is there a timeline / roadmap for this?
m
We could use help if you are interested.
j
Well on the one hand, I would love to help. On the other hand, I don't want to overpromise and underdeliver (which I have a habit of doing...). I have no CMOS experience, but I do have 15yrs software development experience. So it would be a great way to learn about CMOS. But the problem for me is I have a lot of commitments and hence little spare time, but if you give me an idea of how I could help in some way, I'd be happy to contribute something.
m
The first part would actually be learning CMOS and to create a netlist using the OpenRAM API.
If you could get that far, I'm sure I could work out the back end layout.
A good example of the transistor-level API would probably be the column mux: https://github.com/VLSIDA/OpenRAM/blob/dev/compiler/pgates/column_mux.py where you can see that we just define module pins, transistors and their connections in create_netlist. Most of this is going to be software so your skills would be useful. Make a top level script that reads in a file and makes a top level design by instantiating a class derived from the design class. That then has functions to help everything else like the above.
I'd probably make a separate top level called "openrom.py" that creates the ROMs
It should be a decently straight forward project, but I've also got a ton on my plate. I'm definitely willing to advise someone in it though.
j
At the moment I am working on schematic capture for a small 16 bit ROM as a test to learn enough about CMOS roms to do that.
At work we have this thing called "capability days" where we can work on a project out of our own interest, I chose to develop a ROM and a 4-bit current steering DAC and layout and verify them.
I'd be happy to take a look at openRAM and see how it could be done, and ask a few questions perhaps
m
Cool. Where do you work at?
j
I'm from Australia, I work for the Australian government, at a research organisation
I'm an electronics / embedded systems engineer, but we have been working on small wireless communications enabled underwater sensors, and I would like to investigate how feasible it would be to produce a signal processing ASIC that can drive an acoustic transducer in a battery powered sensor.
That's the background
@Matthew Guthaus I have designed a simple 4bit x 4 word ROM using the xschem utility, and posted a screenshot to the #analog-design channel. I wonder if you could help answer some design questions that have arisen from this exercise?
m
Sure. What kind of ROM cell did it use?
j
As in the bit cell? A programmed bit is simply a nfet_1v8 with drain connected to bit lines and gate connected to word lines (source to vss).
👍 1
m
Ok, this is usually called a NOR ROM since all the nfet on a bitline essentially create a NOR gate. (There's also a NAND ROM which can be denser but is slower.)
j
Oh I see! I didn't know that. But I guess it makes a lot of sense (since there is NOR and NAND flash for example). Could you recommend a good text book or some papers on the subject of ROM implementation? My test 16bit design is based on the paper https://ieeexplore.ieee.org/document/1050943 which is very accessible but very out of date
I have access to most journals through work, and ebooks. If its a textbook I don't have access to, I will buy it (textbooks are tax deductible here)
m
There isn't a lot of updated texts because there isn't much money in it. IEEE is probably the way to go.
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