@User I have completed schematic capture and simulation of a 256-bit ROM (16x16). I have a few "capability" days up my sleeve to work on layout. I think it's possible to write a netlist generation script based on this design, as each block in the hierarchy can easily be synthesized according to parameters.

Nice! In OpenRAM, you can make this programmatically using our API. Basically you need to: 1. Create a Python class that is derived from a "design". The design class contains all the attributes you would expect from a schematic sheet (inputs, outputs, instances, submodules, connectivity). 2. The creation occurs in the constructor (the init function) which includes a create_netlist() function and a create_layout() function. 3. A good example of a regular array is the bitcell_array from the SRAM: https://github.com/VLSIDA/OpenRAM/blob/master/compiler/modules/bitcell_array.py 4. The main difference is that you would instantiate individual transistors from the ptx (parameterized transistor) class since this will also create the transistor layout automatically. 5. In the create_netlist() function you will need to create the transistors and connect them with signals. 6. In the create_layout() function you then need to place them. 7. Lastly, you need to devine the height and width of your module so it can be placed with other modules later. The origin should be (0, 0)

Ok great! I will look at OpenRAM today, and based on your hints see what I can do. Thanks!