It's really hard to do the smallest custom layout even disregarding OPC. There are numerous NP hard problems involved.

Maybe my problem with Tim Ansell is that I have not properly conveyed the fact that "there are numerous NP hard problems involved" with automating analog layout. . . : ) I remember working with Fernando Pineda at Johns Hopkins almost 30 years ago; he was working on an analog silicon compiler. The state of the art hasn't moved much since then.

Yeah, that is really what got me interested in EDA. I worked on a CMOS cell generator at an internship at IBM in 1997.