It looks like caravel is using sram_1rw1r_32_256_8_sky130, which is an openRAM macro, correct? There's rtl verilog in the caravel/verilog/rtl directory, but I couldn't find the gate level verilog (was expecting it to be in caravel/verilog/gl). Does the gate level verilog exist for sram_1rw1r_32_256_8_sky130, and if it does, how do I get it?

Gate level doesn't exist for memories. There sounds be a behavioral model.

@Matthew Guthaus Thanks, I'll see if I can find the spice (or extract it).

Actually, that spice may use the old device models as well (before the public release)

Is there any way to get the CDL that you use for LVS?

Isn't it in the repo?

@Matthew Guthaus Are you referring to the caravel repo? If so, there's the

spi/lvs/storage.spi

file, but

sram_1rw1r_32_256_8_sky130

is referenced as a black box. I ended up using the spice extracted from the GDS for CVC(ERC) checks. There was no problem in the sram itself, but at the storage block level some pins were flagged as undriven. (See my message on the caravel channel or Tim's message on the openram channel.)

I was referring to the strive repos. I didn't do anything with caravel and it was the same memory

@Matthew Guthaus Thanks, I'll see if I can locate the strive repos.

sram_1rw1r_32_256_8_sky130.sp,sram_1rw1r_32_256_8_sky130.v

@Matthew Guthaus Thanks for the netlists. I'll see if I can translate the spice file to the sky130A technology that we're using for caravel. Looks like the the model names and parameters don't match as is.

I can always generate a new one since I've updated it to do that. But the new GDS will be fairly different.

@Matthew Guthaus Let me work on it today and get back with you. Shouldn't be too much trouble.

CVC?

Sorry for another TLA (three letter acronym). CVC - Circuit Validity Checker is the ERC-like open source system I developed that we're trying to incorporate into openlane. I did a presentation at WOSET 2020.

Oh yeah, I should go back and watch that fully.