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Is the output data only valid between (negedge clk...
# openram
o
Is the output data only valid between (negedge clk) + DELAY and the next posedge clk ?
m
This is correct
It uses the negative edge to initiate the sense amps
Address decoding is done during the first half of the clock
o
So what is the standard way of reading out from the memories? Can I put a register stage on the outside of the read port that is clocked on posedge?
m
Yes
We are going to add another control module that doesn't use the negative edge but that won't be too soon
You can essentially treat it like a positive edge triggered DFF
o
My simulation still isn't happy. I'm a bit sceptic towards the non-block assignment of dout1. I think that happens before my FF stage has registered the data
I guess we want some kind of hold time after posedge clock before invalidating the output?
Is there some timing diagram available for this? I'm terribly confused right now
Something like this?
m
The address, din, and control bits are internally stored in edge triggered flops
o
The diagram on page 59 is what I would expect, but this is not what happens in the verilog model since d0 becomes X right on the next positive edge (the right-most dotted line).
And I need to read up on the LRM for this, but I think that unlike VHDL, the order of events in verilog are not defined so in my case, the X assignment happens in a delta cycle before I get the chance to read the data
In your diagram it looks like D0 is valid for a whole clock cycle, but in the model it's only valid 1/2 cycle - the DELAY value
m
Ah, yes, the diagram is inaccurate in that way. It will become invalid after the positive edge of the clock when we start to precharge.
This should be a short delay after the positive edge though.
o
That short delay is what I'm after. That would be the hold time. Problem is that it's currently zero in the simulation model. I guess I would also need to know that value for the implementation for the timing analysis?
m
You can add a behavioral value, just like the delay. These are just simulation models only, not accurate.
o
Sure. I don't need them to be super accurate, but without a delay there, nothing can be read from the model. I'll add something there and try to get it upstream as well
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