Hi <@U0175T39732>,
What is the area of 1KB, 4KB, 8...
# openramz
Zeeshan Rafique
04/22/2021, 12:55 PMHi @User,
What is the area of 1KB, 4KB, 8KB and 16KB for SRAM?
Zeeshan Rafique
04/22/2021, 1:19 PMAfter I have the perfect, I can make the decision to choose what size of SRAM should I use in my design...
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Matthew Guthaus
04/22/2021, 6:52 PMsky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8.lef: SIZE 456.66 BY 379.82 ;
sky130_sram_1kbytes_1rw1r_8x1024_8/sky130_sram_1kbytes_1rw1r_8x1024_8.lef: SIZE 432.860 BY 427.420 ;
sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8.lef: SIZE 659.98 BY 398.18 ;
sky130_sram_4kbyte_1rw1r_32x1024_8/sky130_sram_4kbyte_1rw1r_32x1024_8.lef: SIZE 670.86 BY 651.14 ;
8kb and 16kb have been extracting for nearly a day, so I'm not sure yet.
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Zeeshan Rafique
04/22/2021, 8:01 PMThank you !!!
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Matthew Guthaus
04/22/2021, 9:57 PMThis may change too, but for approximation...
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Zeeshan Rafique
04/23/2021, 7:48 AMCould you please point me to the behavioral model of a dual port SRAM (1r1w).
Can I use the 1rw1r SRAM instead of 1r1w SRAM? both will give same functionality?
Zeeshan Rafique
04/23/2021, 11:27 AMI had run the floor planning for this model, but I am getting the area far more than you mentioned above.
https://github.com/efabless/caravel/blob/master/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
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Matthew Guthaus
04/23/2021, 12:36 PMFor now, you can just tie the web of the rw port for the same functionality.
Matthew Guthaus
04/23/2021, 12:37 PMI don't understand what you mean by the area of the verilog....
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Zeeshan Rafique
04/23/2021, 12:38 PMActually this was the model which we are synthesizing and then checking the area after floor plan.
Zeeshan Rafique
04/23/2021, 12:39 PMBTW if I need 16KB of SRAM of 1rw port, is it available yet
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Matthew Guthaus
04/23/2021, 1:10 PMIf you synthesize it, it will be make from flip flops and will have much larger area.
It takes days to create them, so it has been running. Single port is being verified still.
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Zeeshan Rafique
04/27/2021, 12:39 AMOh so what I understand is that we just use the macro instead of synthesizing the RTL of the SRAM.
Zeeshan Rafique
04/27/2021, 12:41 AMSo, for now we are using dual port memory instead of single port bcz its not available yet.
"For now, you can just tie the web of the rw port for the same functionality." ->we will be doing this
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Matthew Guthaus
04/27/2021, 1:53 AMYes, specify the GDS and LEF in the OpenLane scripts and it will use it like a hardened macro.
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