Me and Olof were intending to include an OpenRAM SRAM macro as part of our design in the user project area of Caravel, but the power net generation doesn't seem to work with Openlane tag v0.15. Tested building the storage part of caravel as well to be sure (at tag mpw-two-b), and it gives me the same problem (lots of unconnected PDN nodes). Known issue?

Yes I'm working on this now

Thanks for the update. Working with FF memory synthesized together with the rest of the design instead for the time being

May be I am getting same issue ? why this ports(din0,dout0 and wmask0 ) values is assigned as a don't care in powered netlist? Have you solved this problem ?or you have any idea about this?

@Rameen Anwar this is likely a problem with the instantiation of the memory in your verilog. Can you share that?

@Matthew Guthaus yes,I checked my design. The pin name mentioned as vccd1 and vssd1

@Rameen Anwar you cannot use VPWR and VGND, those must also be vccd1 and vssd1.

@Rameen Anwar that's got to be an issue with synthesis, not the memory, sorry

We are integrating 4KB sram macros and we are facing issue regarding X bit propagation in rtl simulation. We are using inverted clock and the emulation is passing on xilinx FPGA for the Openram behavioral model. Is inverted clock an issue for the X bit propagation in actual macro?

@Rameen Anwar are you using the OpenRAM behavioral model? The inputs are captured on the positive edge and outputs available after the negative edge. The behavioral model outputs x until the data is valid. Inverting the clock would obviously change that to negative and positive clock edges

@Matthew Guthaus question is that. will the inverted clock scenario has an effect on design performance with actual sram macro. we use inverted clock for sram because it gave us improved frequency on FPGA. without any effect on design functionality. does the inverted clock for sram cause any issue with openlane tools for place and route ?? is it fine to go with this case or we have to use same clock for whole design including sram?? can it be cause for x propagation in asic?

I'm not sure about your question, but OpenRAM needs both clock edges to work. Edit: at least with the current replica timing scheme

so, according to behavioral model sram will have x on output at posedge of clock and it will output data after negedge. the behavior will not be effected with any clocking scheme. if am not wrong??

@Sajjad Ahmed that is correct (except if you invert the clock...)