Has anyone established the max size limit of hardened macros generated with OpenRAM that would still fit in the user space? I have a design in mind that would require 64kx8 + 16kx16 SRAMs and am wondering if there is any hope that it would fit. Is there a tutorial on how to quickly establish that short of going through the actual work of hardening the SRAMs? I'm assuming that the DFF equivalents would not fit based on what I've seen on the striVe ICs. TIA!

Nobody has done this.

Let's do some back-of-envelope checks on your proposed instances. I suspect knowledge about how to do basic guesstimates with memory sizing is in short supply, so hopefully this is useful. As a disclaimer, I've only browsed the OpenRAM and may get some facts about it wrong. Indeed, I'm mostly going to be guessing, so anyone can feel free to correct me. Oh, and I'm guessing that when you say "64k" and "16k" you mean powers of 2, not powers of 10. I'm going to use "ki" below (the power of 2 "kibi" prefix) to indicate that. Both your instances are of relatively limited width, which is good, but let's check what happens with column muxing. You usually don't column mux more than 8. So, for you 64kiX8, you cut your rows down to 8ki and up the number of columns to 64. 64 columns isn't inconceivably high, kind of reasonable, actually, so that's good. 8ki rows, though, is huge. For your 16kiX16, you cut your rows down to 2ki and increase your columns to 128. 128 columns is pushing it, but might work. 2ki, more realistic, but still an awful lot of rows. Now, architectures can vary, but you're likely to see a maximum of 64 to 128 rows per bank; maybe 256 in some cases. The number of banks varies, too. A lot of people use 8 banks to an SRAM instance, but I seem to recall OpenRAM uses 4. So, you'd expect your maximum row count to be 256 to 512. Maximum number of columns per bank tends to be 128 to 256. Now, it is possible to go beyond these numbers with horizontal or vertical repeaters. These are relatively rare as they make compiler characterization tricky. It's also usually an either or -- you either have horizontal or vertical repeaters. You could have both, but again, makes characterization tricky and both will be all the trickier. Anyway, repeaters are a pretty advanced feature and I'm pretty sure OpenRAM doesn't have them. So, it's impossible. We can all quit the profession because local caches can't possibly be bigger than a few kibibits, therefore all the processors that have come out for 3 or 4 decades must be an illusion, right? Well, no. It just means you have more work to do. You are going to need to create a memory controller to gang a set of OpenRAM instances together to get your 10s of kiB worth of SRAM. Perhaps this has been done for some RISC-V processor out there already? Otherwise, I guess we'll need an OpenRAMCtrlr project to complement OpenRAM.

We support column muxing of 16.

Thanks for the thorough response @Vern