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1. Why is the data width 33?
# openram
m
3. Why is the data width 33?
m
The single port array requires an even number of cells in a row (and column) due to the lithography of the bitcell. We need one column for the self timing which means there needs to be an odd number of data columns. We are planning to do a non self timed version of the control logic but it will be less reliable to variations. However it won't require the extra column
m
so does the openram macro require some additional controller to run the timing test? that's why the additional bit is exposed on the interface?
m
No. There are technically two bits added, we use one and just expose the other one.
By the way, the dual port does not have this issue.
m
I'm still not getting it, sorry!
m
We need a column of the array for our control logic. But, the bitcell requires that the array be multiples of 2, so we have to add 2. The extra column is just there and can be used or ignored.
m
ah, so we can actually store more data than advertised using the 33rd bit.
but I could just not connect it and keep it 32.
m
Correct.
m
would make a good clickbait video title: "why does this memory have a 33 bit data width?" !
m
Actually, it's a bit more complicated though. If there are more than one word per row in the array, that extra bit would be shared among every word. So it's not 1 bit per word...
It's 1 bit per ~array~row
m
so in the case of 32x256 we have an extra 256 bits accessible with that 33rd databit
m
Errr no...
It depends on the number of words per row. The 256 says how many words are in the memory but not the organization.
According to the run log, the 32x256 has 4 words per row. So there are actually 256/4 = 64 rows. So there are 64 extra bits.
The organization is selected to balance the delay of the word lines and bit lines. I.e. to keep it "square" to the first order
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