I'm wondering if in the SRAM verilog models the "#(T_HOLD) dout0 = 32'bx;" and the "#(T_HOLD) dout1 = 32'bx;" make a lot of sense. When the outputs are registers, why should the value change (become X) depending on the non-relevant edge, or any time thereafter ? What if I connect them to negedge FFs ? (Besides that, though it is a simulation model, it is not a good practice to assign to the same signal in two different processes). But I like the fact that Xilinx reads them and uses BRAMs for it - though I haven't tested it in-system. Cheers, Tobias PS: Besides that, we couldn't build mini-socs without them, so thanks for providing them.

The output is not a register. It is a buffered output from a sense amplifier.

Coming back to this point. After reading the docs, I understand that the sram outputs are not registered. But all I looked at was the verilog model, and it is quite misleading, because the outputs are registered with the negative edge. If you do the model timing accurate, then I don’t understand why you make the behavior timing dependent of the user-defined clock period. The main critical point here is that it can lead to an RTL/silicon mismatch, when the user captures the outputs with a neg-edge. Same problem when the user clocks the sram with the neg-edge of the design clock. So I’m just trying to contribute here and I can be totally wrong with that, but I recommend to look into this issues again, eventually. Cheers, Tobias

I'm not sure I understand your point. The user won't be able to capture timing with a negative edge unless they insert some manual delays but that is always a bad idea at the RTL level...

@User Do we know what's max frequency for OpenRAM 1kB manufactured in sky130? If behavioral model is in tact with hardware, we can imply max frequency to be the same, right or wrong?

We don't really know. The behavioral model is NOT indicative of realistic timing.

@User Happy new year. May I kindly ask the following question ? I stumbled over the statement, that the outputs are not registered, as it is indicated in the verilog model. I think the following statement is correct: Statement 1: The output become valid after a delay (DELAY) relative to the negative edge of the input clock. So the negative-edge sensitive logic, which I generously placed at the output of the SRAM, is actually part of its control logic. But there is also another statement: Statement 2: The output becomes invalid after a delay (T_HOLD) relative to the positive edge of the input clock. Are both statements correct ? Thank you for your reply.

@User a better way to think about it is that the SRAM has two stages. The first half clock cycle is the address decode and array precharge and the second half is the array read (or write) Yes, the output behaves like the verilog model. It becomes valid a DELAY after the negative edge and becomes invalid after a T_HOLD after the positive edge (the precharge activates).