Hi folks, I'm trying to generate an 1w1r_32x32 and (more importantly) an 1w1r_16x32 sram with openram for MPW-4, but get the following error. Any help is highly appreciated. Cheers Tobias |==============================================================================| |========= OpenRAM v1.1.19 =========| |========= =========| |========= VLSI Design and Automation Lab =========| |========= Computer Science and Engineering Department =========| |========= University of California Santa Cruz =========| |========= =========| |========= Usage help: openram-user-group@ucsc.edu =========| |========= Development help: openram-dev-group@ucsc.edu =========| |========= Temp dir: /tmp/openram_tobi_11902_temp/ =========| |========= See LICENSE for license info =========| |==============================================================================| ** Start: 12/27/2021 141859 Technology: sky130 Total size: 1024 bits Word size: 32 Words: 32 Banks: 1 Write size: 8 RW ports: 1 R-only ports: 1 W-only ports: 0 DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). DRC/LVS/PEX is disabled (check_lvsdrc=True to enable). Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). Only generating nominal corner timing. ERROR: file design.py: line 46: Custom cell pin names do not match spice file: ['BL0', 'BR0', 'BL1', 'BR1', 'WL0', 'WL1', 'VDD', 'GND'] vs []

You need to run make install first you fetch the sky130 library.