I have made SRAM test chips in the past. We includ...
# openramf
FatsieFS
01/05/2022, 9:03 AMI have made SRAM test chips in the past. We included there shift registers for address, data in and out; with separate clock for the inputs than the SRAM. Setup and hold times could then be measured by shifting the phase between the clocks.
I'll likely make a test chip for MPW5, an OpenRAM block could be included in there also.
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Matthew Guthaus
01/05/2022, 2:24 PMWe did this for mpw 2/3
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FatsieFS
01/05/2022, 2:29 PMNice, is project publicly accessible ?
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Matthew Guthaus
01/05/2022, 2:38 PMMatthew Guthaus
01/05/2022, 2:39 PMMPW2 had issues because of the parasitics problem in the clock tree that they found in mpw1 caraval too. We fixed that in mpw3.
Matthew Guthaus
01/05/2022, 2:40 PMThey both have a parallel (via the LA) and serial (via GPIO) test mode.
MPW4 we are adding an alternative wishbone test mode in addition where all memories are memory mapped.
Matthew Guthaus
01/05/2022, 2:41 PM(It didn't go through the normal precheck flow which is why it isn't passing there)
Matthew Guthaus
01/05/2022, 2:54 PMThe biggest limitations at this point are that the CTS algorithm still sucks.
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FatsieFS
01/05/2022, 2:56 PMIs this test structure meant to measure setup/hold for address and data and clk2q delay of the SRAM block ?
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Matthew Guthaus
01/05/2022, 3:00 PMNot accurately.
Matthew Guthaus
01/05/2022, 3:02 PMIt's an an iterative process.
First iteration goal was functionality of any memory.
Second was functionality of sizes/ports
Third was to fix CTS bugs
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FatsieFS
01/05/2022, 3:02 PMOK, I'll likely make then one for MPW5; will put selection of your blocks on there also then.
It likely will be custom placement, routing.
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Matthew Guthaus
01/05/2022, 3:02 PMWe missed the fourth because there wasn't enough time with the holidays after mpw3