Hi!
Can someone please help me with the following?
# openrama
Anuj Dubey
02/28/2022, 3:05 PMHi!
Can someone please help me with the following?
👀 1
Anuj Dubey
02/28/2022, 3:11 PMAlso as a follow-up, is there a resource/report somewhere that mentions the area (in mm2) of the synthesized srams with varying sizes? Since efabless shuttles provide a 10mm2 user area, I wanted to estimate how much data can I store before finalizing my design's microarchitecture.
m
Matthew Guthaus
02/28/2022, 4:40 PMHi @User I saw your messages from last night but hadn't had a chance to respond yet. I'll respond here instead of by email too.
1. There is a limit, but we haven't tested it. The SRAMs will stop functioning at some point... There is also a limit to the number of rows due to the decoder levels, but it can be made wider.
2. You need to run "make pdk" and "make install" to get the sky130 library. We are planning a new roll out soon that will make this easier as there might be some bugs in there. We also have a new docker setup that we will use so that you are using the same versions of the tools as us. The other library is from a third party, so I don't know much about it.
Matthew Guthaus
02/28/2022, 4:41 PM@User The datasheets should be in the macros directory which has the sizes.
Matthew Guthaus
02/28/2022, 4:41 PMThey are in html format.
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Anuj Dubey
02/28/2022, 5:06 PMThanks a lot for the response Matthew. Would be great if you could also specify the path from which I should run the make commands. I do not see these targets at least in the Makefile of the top folder: https://github.com/VLSIDA/OpenRAM/blob/stable/Makefile
I believe the macros directory will be built in the technology/sky130A directory after I succeed with the make pdk and make install?
m
Matthew Guthaus
02/28/2022, 5:06 PMIn the root of the openram project
Matthew Guthaus
02/28/2022, 5:07 PMMake sure to use the dev version, this isn't stable so we haven't pushed it to that branch yet
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Anuj Dubey
02/28/2022, 5:08 PMI see! I was using the stable version. Thanks again! 🙂
Anuj Dubey
02/28/2022, 5:26 PMIt also needs the PDK_ROOT variable being set I guess. What should I set it to?
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Matthew Guthaus
02/28/2022, 5:26 PMTo the location of your skywater PDK
Matthew Guthaus
02/28/2022, 5:27 PMMake pdk will put it there if it isn't there
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Anuj Dubey
02/28/2022, 5:28 PMIt didn't apparently. I ran the make pdk and make install commands. And then when I try to compile the SRAM, I get the following error.
python3 $OPENRAM_HOME/openram.py myconfig_sky130.py
Traceback (most recent call last):
File "/home/anuj/OpenRAM_dev/compiler/openram.py", line 35, in <module>
g.init_openram(config_file=args[0], is_unit_test=False)
File "/home/anuj/OpenRAM_dev/compiler/globals.py", line 202, in init_openram
import_tech()
File "/home/anuj/OpenRAM_dev/compiler/globals.py", line 567, in import_tech
tech_mod = __import__(OPTS.tech_name)
File "/home/anuj/OpenRAM_dev/technology/sky130/__init__.py", line 26, in <module>
raise SystemError("Unable to find open_pdks tech file. Set PDK_ROOT.")
SystemError: Unable to find open_pdks tech file. Set PDK_ROOT.
m
Matthew Guthaus
02/28/2022, 5:29 PMYou might need to wait until we release our updates
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Anuj Dubey
02/28/2022, 5:30 PMIs there an approximate date for the release?
m
Matthew Guthaus
02/28/2022, 5:30 PMWorking on it... Not yet. Soon.
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Anuj Dubey
02/28/2022, 5:30 PMGot it. Thanks!
Anuj Dubey
02/28/2022, 5:44 PMI did get past the PDK_ROOT issue by setting it the project TOT based on what I understood from the Makefile. I'll debug this at my end, or probably wait for the release as you're suggesting.
Copy code
** Start: 02/28/2022 12:36:15
Technology: sky130
Total size: 32768 bits
Word size: 32
Words: 1024
Banks: 1
Write size: None
RW ports: 1
R-only ports: 0
W-only ports: 0
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
ERROR: file sram_config.py: line 132: Invalid number of cols including rbl(s): 257. Total cols must be divisible by 2
Traceback (most recent call last):
File "/home/anuj/OpenRAM_dev/compiler/openram.py", line 54, in <module>
c = sram_config(word_size=OPTS.word_size,
File "/home/anuj/OpenRAM_dev/compiler/sram/sram_config.py", line 44, in __init__
self.compute_sizes()
File "/home/anuj/OpenRAM_dev/compiler/sram/sram_config.py", line 95, in compute_sizes
self.recompute_sizes()
File "/home/anuj/OpenRAM_dev/compiler/sram/sram_config.py", line 132, in recompute_sizes
debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, self.array_col_multiple), -1)
File "/home/anuj/OpenRAM_dev/compiler/debug.py", line 47, in error
assert return_value == 0
AssertionError70 Views