Hi Trying to use openram for Sky130 , but below errors are coming : ** Start: 03/01/2022 102731 Technology: sky130 Total size: 32 bits Word size: 2 Words: 16 Banks: 1 Write size: None RW ports: 1 R-only ports: 0 W-only ports: 0 DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). DRC/LVS/PEX is disabled (check_lvsdrc=True to enable). Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). Only generating nominal corner timing. ERROR: file design.py: line 46: Custom cell pin names do not match spice file: ['BL', 'BR', 'VGND', 'VPWR', 'VPB', 'VNB', 'WL'] vs [] Traceback (most recent call last): File "/home/ratul619/IIT_study_VM/OpenRAM/compiler/openram.py", line 54, in <module> c = sram_config(word_size=OPTS.word_size, File "/home/ratul619/IIT_study_VM/OpenRAM/compiler/sram/sram_config.py", line 44, in init self.compute_sizes() File "/home/ratul619/IIT_study_VM/OpenRAM/compiler/sram/sram_config.py", line 73, in compute_sizes bitcell = factory.create(module_type=OPTS.bitcell) File "/home/ratul619/IIT_study_VM/OpenRAM/compiler/sram_factory.py", line 142, in create obj = mod(name=module_name, **kwargs) File "/home/ratul619/IIT_study_VM/OpenRAM/technology/sky130/modules/sky130_bitcell.py", line 29, in init super().__init__(name, cell_name=cell_name, prop=props.bitcell_1port) File "/home/ratul619/IIT_study_VM/OpenRAM/compiler/bitcells/bitcell_base.py", line 21, in init design.design.__init__(self, name, cell_name, prop) File "/home/ratul619/IIT_study_VM/OpenRAM/compiler/base/design.py", line 46, in init debug.check(prop.port_names == self.pins, File "/home/ratul619/IIT_study_VM/OpenRAM/compiler/debug.py", line 33, in check assert 0 AssertionError Do i need to change any further setup ? Thanks

You don't have the PDK setup: https://skywater-pdk.slack.com/archives/C016ULUQXDF/p1646066456202929?thread_ts=1646060752.048439&amp;cid=C016ULUQXDF

my PDK_ROOT points to the area which have below dirs : I am able to run other tools like magic , openlane etc ls /home/ratul619/IIT_study_VM/OpenLane/pdks/ open_pdks sky130A skywater-pdk

Did you run make install?

yes. it was done as a part of the openlane setup. Do i need to do it separately?

This is in OpenRAM not OpenLane

but if i already have the openpdk installed in some other location - cant i reuse it ? Any library version beyond which i will be use the same environment>

This installs the necessary files in the OpenRAM technology directory which uses it's own format and organization.

ok thanks @User