<@U017E7L119N> Digital signal are signal going ful...
# sky130f
FatsieFS
07/12/2020, 1:54 PM@User Digital signal are signal going full swing between GND and VDD; analog signals are circuit typically operating around a certain DC operating point.
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20Mhz
07/12/2020, 3:20 PMsure, from design point of view there are obvious differences. From implementation point of view, an SoC will have both types of circuits, people often refer to this as a digital / mixed implementation flow, however you still need models for the analog parts. I’m not trying to get philosophical just trying to keep it in the context of the original question from mithro on whether the IOs are required.
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FatsieFS
07/13/2020, 9:32 AM@20Mhz @Tim 'mithro' Ansell If one wants to take delays of IO pads into account in timing constraint and STA one needs digital model of IO cell and timing data in the liberty file.
FatsieFS
07/13/2020, 1:46 PMSo to be more explicit, I do think liberty files with timing data for IO cells is needed. I guess it will not before long one wants to be sure a certain output signal has a certain timing with regard to a clock signal.