@User Are you guys providing training to these tools and IPs design? I keep getting these emails/notifications but I am not sure what is the end goal? I am interested in learning more about the riscv part since I have only used ARM cores and SPARC so far.

Openlane Training - coming soon. Till now we used to do with qflow/magic/openSTA ans full RTL2GDS flow Analog IP design training - coming soon for 5-blocks (adc, dac, PLL, bandgap, sram) Training website - https://www.vlsisystemdesign.com/vsd-iat/