I have a few questions about the GDS -> chip proce...
# sky130m
Matt Venn
10/17/2020, 2:52 PMI have a few questions about the GDS -> chip process. I understand the concept of having a GDS file that can be made into a series of masks that are then used to make the chip. This is what we end up with with the sky130 process
✔️ 1
Matt Venn
10/17/2020, 2:52 PMwhy are there so many layers in https://skywater-pdk.readthedocs.io/en/latest/rules/layers.html#gds-layers-information
Matt Venn
10/17/2020, 2:53 PMMatt Venn
10/17/2020, 2:53 PMIs there any information about the order that the layers I see in magic are used and what they relate to in the above 2 links?
Matt Venn
10/17/2020, 2:54 PMI did @Kunal's VLSI course and was expecting maybe 16 masks
Matt Venn
10/17/2020, 2:55 PMlooks like 35 masks in this process?
k
Kunal
10/17/2020, 3:22 PMI used 16 mask CMOS process as a typical example for a certain process. It will vary from process to process
m
Matt Venn
10/17/2020, 3:23 PMI was thinking of doing a version of your slides but specific to the sky130 process.
m
Matthew Guthaus
10/17/2020, 3:30 PMIf you give a layer that you don't know, maybe people can explain it? I don't know all of them but many/most. Sky130 does have a few unique ones it seems.
m
Matt Venn
10/17/2020, 3:55 PM@Matthew Guthaus good idea. OK I've tried to match up what I know here: https://docs.google.com/spreadsheets/d/1y6cjte_stJ96g2f_fNWIj1oU6yipX5GKY3nb_1dL-XE/edit?usp=sharing
Matt Venn
10/17/2020, 3:57 PMI guess there is a lot missing from the picture for one thing
Matt Venn
10/17/2020, 6:04 PMStuff I'm not sure on is in orange, no idea in red
r
Riking28
10/18/2020, 3:26 AMThere have been some photos on Slack of what a deep nwell looks like
Riking28
10/18/2020, 3:26 AMYou can use it to draw a bowl of nwell around a pwell to isolate it
Riking28
10/18/2020, 3:27 AMThere is no deep pwell because the substrate is already p
Riking28
10/18/2020, 3:29 AMThe "high voltage" layers are likely referring to special stuff for the 20V support
f
FatsieFS
10/18/2020, 12:22 PM@User
• No separate mask is needed for a poly gate and field poly. Transistor gates are so-called self aligned by the oxide that is underneath the poly when is goes over an active area. The poly mask is also used to edge away the oxide not under the poly.
• If you have transistors with different threshold voltages (e.g Vth) they will need separate masks for implantation to do the Vth adjustment. This may even be two masks for adjusting the channel under the gate oxide and source/drain implants for adjusting the doping profile of the channel going from source to drain. (NTM, HVNTM, LDNTM)
• Typically the IO transistors have a higher oxide thickness than the core transistors. This needs a mask to be able to process these different oxide thicknesses. (LVOM)
• Active area (also called diffusion) and poly are normally silicided. For (high resistance) resistors parts of them are not silicided. This need an extra step to cover the parts one does not one to be silicided. (RPM)
✔️ 3
m
Matt Venn
10/19/2020, 7:24 AMthanks!
Matt Venn
10/19/2020, 7:27 AMone pair I still can't work out is the local interconnect and then the different connect types. In magic there is li to p, li to n, li to metal.
f
FatsieFS
10/19/2020, 7:38 AMmagic defines via including bottom and top layer. Therefor it has different via for each bottom layer licon can connect to. In gds the top and bottom layers will be merged with the connected wires and the licon of the different vias are also put in one layer.
m
Matt Venn
10/20/2020, 11:33 AMthanks!
p
Philipp Gühring
10/28/2020, 9:20 PM@Matt Venn I added some comments to your document. https://docs.google.com/spreadsheets/d/1y6cjte_stJ96g2f_fNWIj1oU6yipX5GKY3nb_1dL-XE/edit#gid=0
👍 1
Philipp Gühring
10/28/2020, 9:20 PM@Tim 'mithro' Ansell: The glass cut layer seems to be missing in the Masks list: https://skywater-pdk.readthedocs.io/en/latest/rules/masks.html
f
FatsieFS
10/29/2020, 12:14 PM@Philipp Gühring I think it is the Pad layer (PDM).
2 Views