@User, @User, I'd appreciate your input. I am trying to create a layout for a transmission gate without drawing it directly in Magic. My initial approach was to create a verilog module using the verilog switch primitive "cmos", and use OpenLane flow to generate a gds. However, right at the synthesis stage, it appears that Yosys has a problem with the verilog primitives. So now, I am wondering if there is a way I could create a netlist with pfets and nfets from sky130_fd_pr and get the layout from there. My question is can I use sky130_fd_pr this way? And how would I get a layout from such a netlist, since I don't see any .lef or .mag files in this library? If you have suggestions for better approaches to achieve my goal, I'd really appreciate that. Thanks

We have added transmission gate suppory to lclayout about a year ago, so lclayout should be able to generate cells with transmission gates. The HD cells seem to be too dense for lclayout at the moment (I tried hard for the first tapeout), so I would suggest to use a less dense cell layout if you want completely automatic layouting. If you want we can try it together.