i had one small doubt,when i checked the standard cells the width of nmos for inverter of size 1 and nand of size 1 ,they are same,but for equal rise and fall delay we require width of nmos to be of double the size of nmos of inverter right,so how actually we size the mosfets of sky130hd cells,what criteria we follow

so each gate like nand or nor for size x1 should have same width of inverter of that size right

huh, no, it looks like the ratio is the same

yeah

thats a inv_1, inv_2, nand1, nand2

yeah

Im stumped. Hopefully someone else will have some input. Glancing through some papers, it seems that standard cell libraries may no longer optimize for matching rise and fall times because of automated place and route tools and the other sizes may have advantages or something.

yeah actually thanks a lot for ur input,i got some idea

Thanks for asking the question. I was unaware about this too. I am surprised my VLSI class never brought this up 😅

thanks bro

In the picture posted by @Weston Braun in this thread the width of the P transistors are 1.5 times the width of the N transistors as seen by the number of vias in the source and drains (3 for P, 2 for N). The channel length is exactly the same for P and N (150nm drawn, 130nm after all processing steps). Don't let the fact that the length of these transistors happens to be horizontal and the width vertical confuse you

Yes. Assuming the inverter has correctly ratio'ed pmos and nmos width, you would want the width on the nmos for the nand gate to be 2x that of an inverter for equal rise and fall time because there are two nmos in series. That is not the case for the nand gate in the cell library

For proper sizing series transistors you should make the ones closer to ground (for N, or closer to Vdd for P) proportionally larger. Making them the same size as in the picture means that the fall time for input A will not be the same as the fall time for input B, much less match the rise times

This is not something either of us designed. This is from the gds files of the provided sky130 cell library (the spice netlists are also consistent what with is seen in the gds files)

I know - I was just pointing out that the problem is complex and trying to match rise and fall times is just one issue. Here are some nice slides on transistor sizing: http://classweb.ece.umd.edu/enee359a/enee359a-sizing.pdf

Thanks a lot @Jecel Assumpção Jr @Weston Braun. If I'm not wrong, the confusion is because the width is represented vertically?

@Ayush Saran the cells can be mirrored or rotated. So it is best to think of the length as always the direction in which the current flows from the source to the drain and the width the direction orthogonal to that

Oh alright. That clarifies a lot. Thank you!