I've seen a lot of different rules of thumb like PMOS should be

{2x,1.5x,1x}

as wide as NMOS, but I get the impression this depends on the process

Depends on your objective and if you are discussing analog or digital applications.

My objective at present is performance; I'm working in the digital domain

In digital, you care about density or speed. For density you forget about scaling. For speed you want the output rise time to be equal to the output fall time, which then permits the fastest clock. To have a symmetrical output, you want the PMOS drive during the rusing time to equal the NMOS drive in the falling tome. The ratio is process specific, but generally is about 2:1 up to maybe 3:1. Choosing between the two extremes of speed and density depends upon what you are ultimately trying to optimize.

In my experience even the proprietary high speed libraries did not care about the ratio. The high speed version was then with a higher track height or using low-vt transistors. The latter trading of static power consumption for speed. The libraries typically do provide balanced buffers to be used in clock trees; this for keeping the duty ratio of the clock signal.

That's useful to note (though I don't think they count as proprietary in any meaningful sense)

You confuse me, I was talking about the libs provided by TSMC, ARM, ... which definitely are proprietary as in not open-source.

Ah, I thought you were referring to the SKY130 libraries