Hi all, I've worked through the process with a sim...
# sky130m
Mariano Alvira
05/25/2021, 3:42 PMHi all, I've worked through the process with a simple analog only design. It has gone well. I'm running the precheck and the XOR consistency check has been churning for a few days now. Is this normal? Do I need to run this check?
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Tim Edwards
05/25/2021, 3:53 PMNo, that's not normal. Especially for a simple analog design, the precheck and xor should take only minutes.
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Mariano Alvira
05/25/2021, 3:56 PMOk thanks, Ill try to dig in and see what is happening. This is the repo https://github.com/malvira/vlsi-sky130-analog-caravel-test1 test1 branch. The "design" is a common source amp and test resistor. I ripped out the example-pors.
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Tim Edwards
05/25/2021, 3:57 PMYou should post a helpdesk ticket to efabless to see if somebody can track down the pre-check process and figure out why it appears to be stuck.
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Mariano Alvira
05/25/2021, 3:58 PMok thanks!
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John Kustin
05/27/2021, 9:13 PMI just ran into this issue. I found my problem by looking at
caravel_user_project_analog/checks/xor.logJohn Kustin
05/27/2021, 9:14 PMThe STDOUT hangs, but these logs are populated. My xor failed to run because it couldn't find the proper cellname in my .gds.
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Mariano Alvira
05/27/2021, 10:42 PMgreat I will check those tonight. I was looking for them but couldn't find them