Hi there, I'm new at here. I'm following openlane tutorials, and yeah, I have a problem so I have joined 😅 I have a verilog file with no clock on it, only inputs and do something registers inside and outputs. When I try to to synthesize it, it is getting stucked at

5.22.2 Executing OPT_MERGE pass

phase. Here is my config.json:

{
  "DESIGN_NAME": "MY_MODULE",
  "VERILOG_FILES": "./designs/my_module/src/MY_MODULE.v",
  "CLOCK_PORT": "",
  "CLOCK_NET": "",
  "CLOCK_TREE_SYNTH": 0,
  "CLOCK_PERIOD": 0
}

There is no clock, the registers are getting updated by

always @(*)

block. Thanks!

You probably want to post this in the #openlane channel.

yes and post your design. I would guess yosys is choking on your design, so it's nothing to do with openlane. Try to get yosys to synthesise it first. I'd imagine it's having problems with unclocked registered

Oh sorry my bad, thanks for helping.

np