# sky130

Matthew Guthaus

06/12/2021, 9:06 PM
What is the issue with SRAMs? I've seen the router ignoring wide metal spacing rules near the SRAM but there isn't much I can do about that in OpenRAM.

Matthew Ballance

06/13/2021, 2:49 AM
@Matthew Guthaus, not sure if your question was for me. If it was, my question/issue was whether having unconnected sram-macro ports (eg the read-only interface) would create problems. I haven't yet found a way, in Verilog, to tie off unused ports at the top level. Just wondering whether I should be concerned.

Matthew Guthaus

06/13/2021, 5:56 AM
@Matthew Ballance Yes it was for you. You need to at least tie the control signals and clock: csb1=vdd, clk=gnd (or vdd). If not, I'm not sure what would happen..
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