Preet Batavia
07/25/2021, 5:28 PMArman Avetisyan
07/25/2021, 8:36 PMArman Avetisyan
07/25/2021, 8:36 PMPreet Batavia
07/26/2021, 6:33 AMArman Avetisyan
07/26/2021, 7:11 AMArman Avetisyan
07/26/2021, 7:12 AMPreet Batavia
07/26/2021, 9:25 AMArman Avetisyan
07/26/2021, 9:25 AMArman Avetisyan
07/26/2021, 9:26 AMPreet Batavia
07/26/2021, 9:27 AMArman Avetisyan
07/26/2021, 9:27 AMPreet Batavia
07/26/2021, 9:29 AMPreet Batavia
07/26/2021, 9:30 AMArman Avetisyan
07/26/2021, 9:32 AMArman Avetisyan
07/26/2021, 9:33 AMPreet Batavia
07/26/2021, 9:34 AMArman Avetisyan
07/26/2021, 9:35 AMArman Avetisyan
07/26/2021, 9:35 AMPreet Batavia
07/26/2021, 9:35 AMArman Avetisyan
07/26/2021, 9:35 AMArman Avetisyan
07/26/2021, 9:36 AMArman Avetisyan
07/26/2021, 9:36 AMArman Avetisyan
07/26/2021, 9:37 AMPreet Batavia
07/26/2021, 9:37 AMArman Avetisyan
07/26/2021, 9:38 AMArman Avetisyan
07/26/2021, 9:38 AMPreet Batavia
07/26/2021, 9:39 AMArman Avetisyan
07/26/2021, 9:42 AMPreet Batavia
07/26/2021, 9:42 AMPreet Batavia
07/26/2021, 9:43 AMmodule test1(out, a, b, c, d, s0, s1,clk);
output out;
input a, b, c, d, s0, s1,clk;
wire s0bar, s1bar, T1, T2, T3, T4;
not (s0bar, s0), (s1bar, s1);
and (T1, a, s0bar, s1bar), (T2, b, s0bar, s1),(T3, c, s0, s1bar), (T4, d, s0, s1);
or(out, T1, T2, T3, T4);
endmodule
This is the verilog RTL script for muxPreet Batavia
07/26/2021, 9:44 AMmodule muxt_b;
reg a;
reg s0;
reg s1;
reg clk;
reg b;
reg c;
reg d;
wire out;
test1 uut (.a(a),.b(b),.c(c),.d(d),.s0(s0),.s1(s1),.out(out));
initial begin
a = 1'b1;
b = 1'b0 ;
c = 1'b1;
d = 1'b0;
#10 s0=1'b0;
s1=1'b0;
#10 s0=1'b0;
s1=1'b1;
#10 s0=1'b1;
s1=1'b0;
#10 s0=1'b1;
s1=1'b1;
#10 $stop;
end
endmodule
Preet Batavia
07/26/2021, 9:44 AMPreet Batavia
07/26/2021, 9:45 AMiverilog -o my_design mux_test.v design.v
Preet Batavia
07/26/2021, 9:45 AMArman Avetisyan
07/26/2021, 9:46 AMArman Avetisyan
07/26/2021, 9:46 AMPreet Batavia
07/26/2021, 9:46 AMArman Avetisyan
07/26/2021, 9:47 AMPreet Batavia
07/26/2021, 9:47 AMArman Avetisyan
07/26/2021, 9:47 AMPreet Batavia
07/26/2021, 9:50 AMArman Avetisyan
07/26/2021, 9:52 AMArman Avetisyan
07/26/2021, 9:52 AMPreet Batavia
07/26/2021, 9:54 AMPreet Batavia
07/26/2021, 9:55 AMArman Avetisyan
07/26/2021, 9:55 AMPreet Batavia
07/26/2021, 10:09 AMPreet Batavia
07/26/2021, 10:10 AMPreet Batavia
07/26/2021, 10:12 AMPreet Batavia
07/26/2021, 10:13 AMPreet Batavia
07/26/2021, 10:25 AMArman Avetisyan
07/26/2021, 10:38 AMiverilog -o my_design mux_test.v design.v
You need to modifyit this way:
iverilog -o my_design mux_test.v gatelevel.v gatedefinitions.v
Arman Avetisyan
07/26/2021, 10:38 AMArman Avetisyan
07/26/2021, 10:39 AMArman Avetisyan
07/26/2021, 10:53 AMPreet Batavia
07/26/2021, 11:03 AMPreet Batavia
07/26/2021, 1:56 PMArman Avetisyan
07/26/2021, 2:38 PMArman Avetisyan
07/26/2021, 2:39 PMPreet Batavia
07/26/2021, 2:41 PMPreet Batavia
07/26/2021, 2:45 PM`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
wire 1 ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
assign awake = ( VPWR === 1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
Preet Batavia
07/26/2021, 2:46 PMPreet Batavia
07/26/2021, 2:46 PMPreet Batavia
07/27/2021, 7:01 AMArman Avetisyan
07/27/2021, 8:08 AMArman Avetisyan
07/27/2021, 8:09 AMPreet Batavia
07/27/2021, 8:23 AMPreet Batavia
07/27/2021, 8:25 AMArman Avetisyan
07/27/2021, 12:21 PMPreet Batavia
07/27/2021, 12:22 PMPreet Batavia
07/27/2021, 12:39 PMPreet Batavia
07/27/2021, 12:39 PMPreet Batavia
07/27/2021, 2:57 PMPreet Batavia
07/27/2021, 2:57 PMArman Avetisyan
07/28/2021, 1:14 PMArman Avetisyan
07/28/2021, 1:14 PMPreet Batavia
07/28/2021, 3:34 PMPreet Batavia
07/28/2021, 3:34 PMPreet Batavia
07/28/2021, 3:35 PMPreet Batavia
07/28/2021, 3:37 PMArman Avetisyan
08/02/2021, 7:09 AMPreet Batavia
08/02/2021, 6:38 PMiverilog -o -DPOWER_PINS my_design3 mux_open.v test1_synthesis_preroute.v gate_def.v
Preet Batavia
08/02/2021, 6:38 PMPreet Batavia
08/02/2021, 6:39 PM