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#sky130
Title
# sky130
p

Preet Batavia

07/25/2021, 5:28 PM
Openlane has created a .spice file for me , on invoking it using ngspice , i am unable to see any nodes and corresponding voltages.Need help here.
a

Arman Avetisyan

07/25/2021, 8:36 PM
Openlane as far as I know creates the .subckt which is definition of your model
Then you have to create a testbench, which is usually done in Verilog using Icarus Verilog and gatelevel simulation instead of NGSPICE, because spice is slow.
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Preet Batavia

07/26/2021, 6:33 AM
ohhh cool , ill try that out
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Arman Avetisyan

07/26/2021, 7:11 AM
Sorry, let me clarify it further: Usually when you have an RTL, you do an testbench with your RTL. Then you do openlane and get .spice and gate level verilog Now you have two options: Create testbench in ngspice with .spice from openlane OR create testbench with verilog and run it on with gate level verilog file. NGSPICE is extremly slow compared to gate level simulation
If you are using caravel user project there is ready to use testbenches and examples w/ makefile that does gate level simulation for you.
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Preet Batavia

07/26/2021, 9:25 AM
as of now i am not using caravel user project . So currently as you said , i created a test bench for the mux which i will run it against the verilog file i wrote for the mux . Am i right ?
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Arman Avetisyan

07/26/2021, 9:25 AM
There at least two verilog files for your mux: RTL (what you wrote) and Gatelevel (what openlane created)
You can run using both, but in this case to achieve what you want, you probably want to use the Gatelevel
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Preet Batavia

07/26/2021, 9:27 AM
yeah so i wrote one verilog script for the mux , feeded it to openlane to which openlane created a .spice file defining a number of sub circuits in it.
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Arman Avetisyan

07/26/2021, 9:27 AM
It also created a .v file
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Preet Batavia

07/26/2021, 9:29 AM
yes true
so that is the gate level right ?
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Arman Avetisyan

07/26/2021, 9:32 AM
What is name of that file?
Because not all .v files are equal. Some are gate level, some are optimized gate level
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Preet Batavia

07/26/2021, 9:34 AM
so my design name is test1 , and the name of the file is : /home/preet/OpenLane/designs/test1/runs/23-07_04-55/results/synthesis/test1.synthesis_optimized.v
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Arman Avetisyan

07/26/2021, 9:35 AM
Honestly I don't know which one is the best one in this case, but yes it is the gatelevel
Now you need to include gate definitions (ones defines as modules not as primitives)
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Preet Batavia

07/26/2021, 9:35 AM
ohhh cool
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Arman Avetisyan

07/26/2021, 9:35 AM
Into your testbench
Without it it will complain about Gate module definitions missing
It's usually in sky130A/libs.ref folder in your PDK ROOT
sorry I mean $(PDK_ROOT)/sky130A/libs.ref/$(STD_CELL_LIBRARY)/verilog/$(STD_CELL_LIBRARY).v
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Preet Batavia

07/26/2021, 9:37 AM
so just for now what i did was i ran a simple testbench against the RTL code for mux in iverilog , it created some output script , is there a way to visualize it in some GUI
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Arman Avetisyan

07/26/2021, 9:38 AM
Use GTKWAVE to open .vcd files
It's free and it's availible for Win/Linux/Mac and on some distros as ready to use package
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Preet Batavia

07/26/2021, 9:39 AM
iverilog created a plane .txt doc
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Arman Avetisyan

07/26/2021, 9:42 AM
can you post the testbench and iverilog invocation command?
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Preet Batavia

07/26/2021, 9:42 AM
sure
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module test1(out, a, b, c, d, s0, s1,clk);

output out;
input a, b, c, d, s0, s1,clk;
wire s0bar, s1bar, T1, T2, T3, T4;

not (s0bar, s0), (s1bar, s1);
and (T1, a, s0bar, s1bar), (T2, b, s0bar, s1),(T3, c, s0, s1bar), (T4, d, s0, s1);
or(out, T1, T2, T3, T4);

endmodule
This is the verilog RTL script for mux
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module muxt_b;

reg  a;

reg  s0;
reg s1;
reg clk;


reg b;
reg c;
reg d;


wire out;

test1 uut (.a(a),.b(b),.c(c),.d(d),.s0(s0),.s1(s1),.out(out));

initial begin


a = 1'b1;

b = 1'b0 ;

c = 1'b1;
d = 1'b0;

#10 s0=1'b0;
s1=1'b0;

#10 s0=1'b0;
s1=1'b1;

#10 s0=1'b1;
s1=1'b0;

#10 s0=1'b1;
s1=1'b1;	



#10 $stop;

end

endmodule
THis is the testbench
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iverilog -o my_design  mux_test.v design.v
this is the iverilog invocation command
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Arman Avetisyan

07/26/2021, 9:46 AM
Iverilog is a tool that generates a netlist representation (-o my_design) of your verilog files
Now you need to run the netlist using VVP
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Preet Batavia

07/26/2021, 9:46 AM
So it basically created a txt file named my_design
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Arman Avetisyan

07/26/2021, 9:47 AM
Yes, it's the netlist
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Preet Batavia

07/26/2021, 9:47 AM
ahh okay okay
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Arman Avetisyan

07/26/2021, 9:47 AM
The VVP netlist
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Preet Batavia

07/26/2021, 9:50 AM
It is initiating some console of its own i suppose
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Arman Avetisyan

07/26/2021, 9:52 AM
Note: You should include $dumpfile $dumpvars so the VVP can generate .vcd file Also: $stop calls the console, $finish finishes the simulation
Also note that you are running RTL simulation because you supplied RTL module definition not .v gatelevel
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Preet Batavia

07/26/2021, 9:54 AM
yeah true , this was just for a try , ill try it out in the gate level file created by openlane once this works
btw where should i add dumpfile and dumpvars , in the testbench right ?
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Arman Avetisyan

07/26/2021, 9:55 AM
Yes in initial begin here end
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Preet Batavia

07/26/2021, 10:09 AM
yeah a .vcd file is created
on opening it with gtkwave , there is no waveform being displayed
ohhh sorry , had to insert those in the GUI , it worked
perfect , so once this is done , i need to do the same on the gate level netlist right , which is created by openlane
just one more question , you spoke about adding gate definitions in the testbench, can you explain it again
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Arman Avetisyan

07/26/2021, 10:38 AM
YOu are invoking it like this:
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iverilog -o my_design  mux_test.v design.v
You need to modifyit this way:
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iverilog -o my_design  mux_test.v gatelevel.v gatedefinitions.v
Where gateleve.v is path to gatelevel module definition
And gatedefinition.v is file defining your gates for example: $(PDK_ROOT)/sky130A/libs.ref/$(STD_CELL_LIBRARY)/verilog/$(STD_CELL_LIBRARY).v Please note that the variables need to be properly set or replaced with correct values
Also: .preroute.v is the most full gatelevel I would assume
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Preet Batavia

07/26/2021, 11:03 AM
THank you so much for the support , ill try and get back to you
im getting this error :
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Arman Avetisyan

07/26/2021, 2:38 PM
What version of openlane are you using? Why are you not using Iverilog from OpenLane?
Can you send relevant section of .v code?
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Preet Batavia

07/26/2021, 2:41 PM
will it make a difference if i run it from openlane or outside it
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`timescale 1ns / 1ps
`default_nettype none

// Import user defined primitives.

`celldefine
module sky130_fd_sc_hd__dlxbn (
    Q     ,
    Q_N   ,
    D     ,
    GATE_N
);

    // Module ports
    output Q     ;
    output Q_N   ;
    input  D     ;
    input  GATE_N;

    // Module supplies
    supply1 VPWR;
    supply0 VGND;
    supply1 VPB ;
    supply0 VNB ;

    // Local signals
    wire GATE          ;
    wire buf_Q         ;
    wire GATE_N_delayed;
    wire D_delayed     ;
    reg  notifier      ;
    wire awake         ;
    wire 1             ;

    //                                    Name     Output  Other arguments
    not                                   not0    (GATE  , GATE_N_delayed                       );
    sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
    assign awake = ( VPWR === 1 );
    buf                                   buf0    (Q     , buf_Q                                );
    not                                   not1    (Q_N   , buf_Q                                );

endmodule
`endcelldefine
wire 1 ;
is the line with error
Any work around to this issue ?
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Arman Avetisyan

07/27/2021, 8:08 AM
1. What version of everything are you using 2. If it's latest or is reproducible in latest then report it as an issue
I think somebodye already reported it, somebody mentioned this.
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Preet Batavia

07/27/2021, 8:23 AM
yeah even i saw it , someone has reported a similar issue with iverilog
I am using v0.15
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Arman Avetisyan

07/27/2021, 12:21 PM
Hmm... Can you find a link to the issue? can't seem to find it
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Preet Batavia

07/27/2021, 12:22 PM
ill have to look it up again ... i try finding it
im unable to find it
though i have posted the issue
i found the solution , had to comment out wire 1 ; in the .v file
but now after that this is the error i am facing :
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Arman Avetisyan

07/28/2021, 1:14 PM
YOu have to set the `define POWER_PINS
which forces this pins to exist
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Preet Batavia

07/28/2021, 3:34 PM
ohhh ohhk
ill try that out
in the same verilog files where we are including the libraries right ?
oh no wait i suppose in the testbench right ? , can u tell me exactly what will be the line and where to add it ?
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Arman Avetisyan

08/02/2021, 7:09 AM
It should be done in Iverilog parameters. I think -DPOWER_PINS should do it
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Preet Batavia

08/02/2021, 6:38 PM
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iverilog -o -DPOWER_PINS  my_design3  mux_open.v test1_synthesis_preroute.v gate_def.v
This is my command
THis is the error : mux_open.v test1_synthesis_preroute.v gate_def.v my_design3: No such file or directory No top level modules, and no -s option.