I was just getting my hands dirty on a small design with OpenLANE. Just copy-pasted a basic mux design in verilog:

module m21(Y, D0, D1, S) 
  output Y;
  input D0, D1, S;
  wire T1, T2, Sbar;
 
  and (T1, D1, S), (T2, D0, Sbar);
  not (Sbar, S);
  or (Y, T1, T2);
endmodule

and used the

config.tcl

file generated from

-init-design-config

flag. I am getting an error related to the number of voltage sources being 0. I have attached a screenshot for the reference.

probably because the power grid is too small to be effective

Okay thanks!

Also, does the Verilog define the power pins? You need to add conditional pins like this: `ifdef USE_POWER_PINS inout vdda1, // User area 1 3.3V supply inout vdda2, // User area 2 3.3V supply inout vssa1, // User area 1 analog ground inout vssa2, // User area 2 analog ground inout vccd1, // User area 1 1.8V supply inout vccd2, // User area 2 1.8v supply inout vssd1, // User area 1 digital ground inout vssd2, // User area 2 digital ground `endif

I think that's optional isn't it? default power ports will be added if none exist

Ah, I didn't know that since it is in the user_proj_example.v

very few of the openlane examples use it

No I don't have this in my small mux design since it is not intended to be integrated inside caravel

set ::env(FP_SIZING) "relative"                                                                                                                                 
set ::env(FP_CORE_UTIL) "10" 
set ::env(PL_TARGET_DENSITY) "0.80"

Try adding these to config.tcl

This FAQ entry may be helpful too: https://github.com/The-OpenROAD-Project/OpenLane/wiki#how-to-add-a-small-design (last paragraph briefly addresses PDN issues)

@Preet Batavia after setting the FP_CORE_UTIL as above the design progressed further. However, now I am getting LVS errors. Seemingly there are mismatches related to decap cells. I have attached the log file for reference.