I’m working on a design using the Skywater IO cells, and noticed that Magic finds a lot of DRC errors within the cells themselves. Is that expected? (I figure I can abstract them out similarly to how the OpenRAM memories are abstracted out by the OpenLANE flow)

Yes. The I/O cell layouts were done in a way that gives magic fits, with diffusion and implants, and contacts and metal, split across multiple levels of hierarchy. It takes a bit of work to read them in from GDS so as to be able to get a layout that is valid enough to extract (mostly---even that has issues of deep nwell structures in different cells that splits substrates across multiple levels of hierarchy). Getting that to read in to be DRC clean was more hassle than it was worth. Instead, I use abstract views of the I/O pad cells for checking DRC (same with the SRAM cells). The only good solution to this would be to redraw the I/O cell layouts to reorganize them into a more sane hierarchy.