Can we design oscillator in openlane

Oscillators are difficult for STA because of the combinational loop. But there are ways to deal with it. You can't synthesize an oscillator, but you can implement it with a verilog netlist. See the

digital_pll.v

in Caravel. It is a programmable ring oscillator, and it gets synthesized into the Caravel management SoC core by openlane.

Thank you