Sorry for the clueless question, is there a mechanism for extracting wire parasitics from OpenRoad Sky130 flow and doing static timing analysis? And is there something on the roadmap for doing open source simulation with parasitics?

All of your questions are very relevant, not clueless at all! OpenRCX is now part of OpenROAD, a very recent addition. The lack of OpenRCX at the time we did MPW-one was the main reason that we were lacking all awareness of the severe timing issues in the management SoC. We are now getting it integrated into the Openlane flow. And there is a commercial open-source verilog simulation tool called "cvc" that will do simulation with parasitics extracted by OpenRCX (iverilog doesn't).