I'm wondering to know if it's technically possible to design multi-level memories using Sky130?
11/20/2021, 10:52 PM
Sure, but challenging!
11/20/2021, 11:30 PM
Definitely possible (but as said, challenging) for flash cells, I don't think it is possible for SRAM cells, it is possible (although extremely difficult) for Dynamic RAM.
It is worth noting that sky130 is not an advanced process node, so any memory implementation will not be even close to densities that are achieved with current aggressive process nodes. Moreover a multilevel sensing usually trades speed for density.
Memory macros are usually placed as support modules for digital ASICs (processors, DSPs), using 1 bit /cell allows to use well known generators and reliable implementation.
11/21/2021, 3:32 AM
I was thinking about a PIM (Processing In Memory) technology for Deep Learning Accelerators. So you mean despite the challenges and difficulties to design such cells (specifically DRAM), it is not worth it, right?
11/22/2021, 8:49 AM
Nobody can say something is not worth doing. Innovation is achieved by doing "insane" things!!, so if you have good ideas go for that!!