Hi, I got this error "Can't open ABC output file" when running "abc -liberty cells.lib" on Yosys. Is it because of using "cells.lib"? How to fix it? When I run it directly after "read_verilog" before "synth -top" I got "skipping model as it contains processes" I can't understand it, any explanation, please? What is the command to download libs (sk130) I only have "cells.lib", please?

https://github.com/The-OpenROAD-Project/OpenLane#setting-up-openlane

make pdk

will download automatically