Hi, How does the sizing work for NMOS and PMOS devices? I originally thought the sky130 meant the smallest channel length would be 130nm, but it seems that devices like nfet_01v8 have a default L of 0.15 in xschem. Is that shortest length, or is it okay to change it to 130nm?

The 150nm is the minimum length (however, I struggle to find this in the docs). SKY130 looks like a half node of 180nm, which corresponds roughly to the description here, calling it a “180-130 hybrid technology”. https://skywater-pdk.readthedocs.io/en/main/rules/background.html

@User Thanks. I see the high voltage fet min gate width is 0.5 um. Is there a min gate width document for non-high voltage fets?

its 0.15. The 0.13 is for sram cells only, but they have fixed layout

@User: The minimum transistor width for low-voltage devices is 0.42um. However, SkyWater's designs use 0.36um wide devices in standard cells and 0.21um wide nFET devices and even 0.14um wide pFET devices in the SRAM cells. This mostly has to do with reliability, variation, and characterization. The standard cells are well characterized and devices need only be in the "on" or "off" state, so wide variation in behavior among devices is tolerable. SRAM cells are very small and created in huge arrays, so the regularity of the layout improves matching considerably and allows devices to be much smaller than they could be outside of such a dense and regular array.

@User Sorry, I think I switched the terms throughout the thread, but I was trying to find the minimum length (instead of width) possible for these devices? Is it 0.15 um (for nfet_g1v8) and whatever is the default for other higher voltage devices when you first load a device in xschem?

The rules are 0.15um minimum length for 1.8V devices, and 0.50um minimum length for the 3.3-5V devices.

Okay, thanks so much!

I hear that the process node names 130nm, 12nm, 5nm, etc. don't really correspond to any physical property on the layout anymore.

It's all marketing. . . and sometimes fudging the numbers so it looks like you're still keeping up with (RIP) Moore's Law.

Down to 28nm node the name is roughly equal to critical dimension, mostly minimum channel length. Below 28nm that relationship broke, and Lmin is not tracking node name any longer.

To be fair, SkyWater advertises the process as a "hybrid 130 / 180 nm", but I don't really know if that means anything, either (normally it would mean front-end / back-end).

In 130nm technology nodes, the gate length was really 130nm. Calling this technology sky130 is a a marketing ploy.

This clarifies things for me too; thanks for having this discussion.