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#sky130
Title
# sky130
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Darío San Martín Molina

03/02/2022, 12:43 PM
Hi, is it possible AND safe (from the point of view of reliability & lifetime) to drive Sky130 logic standard cells at a relatively high speed such as, for example, 3.8GHz or 4GHz approx? For example, cells like clock buffers such as
sky130_fd_sc_hd__clkbuf_1
,
sky130_fd_sc_hd__clkbuf_2
,
sky130_fd_sc_hd__clkbuf_4
,
sky130_fd_sc_hd__clkbuf_8
,
sky130_fd_sc_hd__clkbuf_16
, cells like inverters and other logic cells like
sky130_fd_sc_hd__inv_1
, __inv2_2, ___inv__4, ___inv__8, ___inv__16, etc... These cells have minimum length devices (0.15um) inside them. Is it safe to run them at something like 3.8GHz or 4GHz (for example from a high speed VCO), or would there be a reliability/lifetime risk due to degradation effects that could break the device due to the high speed switching for long periods of time?
h

Harald Pretl

03/02/2022, 12:57 PM
A simple answer is that switching speed does not "hurt" the MOS-FET, as long as you stay inside a safe operating area. What can degrade a MOS-FET is a high voltage (dielectric breakthrough, hot electrons) and/or high-current (electro-migration). Generally, high temperature accelerates degradation effects. So the main question is: Which voltages do you want to apply? Here is a description of effects: https://skywater-pdk.readthedocs.io/en/main/rules/hv.html#failure-mechanisms-in-high-voltage-devices For the low voltage MOS-FET stay below 1.95V
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Darío San Martín Molina

03/02/2022, 1:04 PM
My circuit operates with VDD=1.8V (typical, maybe up to around 1.98V in high supply corner) and all my devices are currently _01v8 devices. The kind of voltages that appear at the output of my VCO look like this, for VDD=1.8V it spikes a bit above 1.8V as seen below:
Ultimately my question I'm trying to answer is this: is it safe to have 0.15um length devices in my design, under said circumstances? (Meaning that, if my devices are 0.15um in those conditions, should I be worried that my VCO will "break" after something like a week of use?) And therefore, should I make my high speed switching devices larger like for example 2x min_length (so around 0.3um length), which would therefore make my VCO slower and I would have to redesign it and/or increase current to recover the speed, etc?
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Harald Pretl

03/02/2022, 1:13 PM
This looks good. Usually, silicon technology is qualified for a lifetime (usually 10yrs, maybe more), at least consumer temperature profile (-30C..125C), and voltages <1.95V.
No need to increase Lmin. It is quite customary to stress devices in VCOs up to 2xVmax (but this needs an exact reliability calc), as VCO performance increases, and an AC voltage causes less reliability issues than DC.
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Darío San Martín Molina

03/02/2022, 1:22 PM
Thanks for your input Harald. I've heard in some contexts that there is a certain line of thought that tends to recommend making all devices switching at relatively high speeds (the order of magnitude we are talking here) making them all at least 2x Lmin and 2x Wmin, the idea behind this thinking would be that such larger devices would be more resistant to these breakdown effects and hence more resilient against reliability/lifetime issues. As I understand from your previous comment, it sounds like this recommendation may be perhaps a bit too convervative (potentially good for safety, but perhaps a bit too much on the convervative side)?
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Harald Pretl

03/02/2022, 5:10 PM
I think making devices artificially larger than needed is counterproductive, especially for high frequency. If you go to 2L and 2W, you have made the Cgs 4x larger, which means power consumption to drive this cap goes up tremendously, which causes more heating, and heating is bad for reliability, and obviously total power consumption, which is always a concern. So no, as long as you're in a safe operating area you are good, no need to size devices up in my view. If you find literature that shows otherwise I would be interested to study it.
As a general rule: Keep MOS-FET at Lmin as long as no good reason speaks against it. In every CMOS technology, the devices are optimized at Lmin, because that is what the digital uses. And digital pays the bill for technology development :-)
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Darío San Martín Molina

03/02/2022, 5:36 PM
Totally agree. Thanks! 👍👋
Hi Harald may I borrow your wisdom for another related question: What problems would you see with using LVT devices in a Current starved VCO core? (VDD=1.8V nominal) Goal would be to increase frequency of operation even if power consumption goes up. As LVT devices turn on earlier than standard VT ones, delay cells within the VCO switch faster hence faster VCO switching frequency overall. Any fundamental drawback with using LVT devices rather than standard ones? Apart from higher leakage, etc. Thanks
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Harald Pretl

03/03/2022, 10:07 PM
There is no fundamental difference in the MOS-FET with different Vth, just the Vth 🙂 (and Vth is tuned via different channel implant dose, or work function in FinFET). So choose whatever fits your needs, and using the LVT in analog circuits is quite common. Of course, there is the increased Ids leakage current when Vgs=0V, but in a current-starved VCO this does not matter much, since you turn off the block via the current sources, I assume.
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Darío San Martín Molina

03/04/2022, 12:12 PM
Thanks Harald 👍!!!