Hello I am trying to synthesize my design using openlane and open-source-silicon #sky130

Channels

caravel-documentation

mpw-6plus-silicon

pd-openlane-and-sky130

chipignite2206q_stanford_bringup

cadence-virtuoso

fossee-iitb-esim

dynamic-power-estimation

ieee-sscs-dc-23

gfmpw-0-silicon

silicon-validation

fossee-iitb-google-sky130

ieee-sscs-dc-22

mpw-one-silicon

cadence-innovus

verification-fe

foss-asic-tools

openpositarithmetic

openadiabaticlogic

hardware-beginners

design-services

private-shuttle

tapeout-pakistan

rad-lab-silicon

cadence-spectre

mpw-one-clean-short

coalition-for-digital-environmental-sustainability

vlsi_verilog_using_opensource_eda

vlsi_verilog_using_opensoure_eda

openlane_cloudrunner

digital-electronics-learners

verilog-learners

open-microelectronics-textbook

mwcas-2023-rtl2silicon

system-verilog-learners

vlsi-learners-group

chilechipmakers

silicon-validation-private

openhighqualityresonators

waveform-viewers

vendor-synopsys

silicon-photonics

opendataset-circuitnet-for-ml-tasks-in-vlsi-cad

community_denmark_dtu

shuttle-precheck

openlane-development

ieee-sscs-dc-21q3

sky130-pv-workshop

verification-be

Title

# sky130

j

Jure Vreča

03/17/2022, 11:30 AM

Hello, I am trying to synthesize my design using openlane, and I get an error in placement. In the picture you can see the log: "12-opendp.log". I am new to physical design, so I honestly I am clueless as what is the problem.

I forgot to add the image

Anyway, If anyone has some insight as to why this is happening, I will greatly appreciate the help. Regards, Jure

m

Matt Venn

03/17/2022, 12:14 PM

looks like a config error to me

can you add all the config to a public repo and ask again with a link in the #openlane channel

j

Jure Vreča

03/17/2022, 12:15 PM

Hey Matt, Thanks for the tip, I will do that.