https://open-source-silicon.dev logo
#sky130
Title
# sky130
d

Davide Cavion

03/31/2022, 11:39 AM
What’s the reason most designs seem to be struggling with getting to 100 MHz? The original SkyWater announcement said that Intel brought some 2GHz CPUs to market using a 130nm process, so is this a limitation of the open source tools? Also I saw the #sky65 and #sky90 channels, is something brewing or are we getting ahead of ourselves?
m

Matt Venn

03/31/2022, 12:06 PM
good question. My understanding: • the designs may be large/complicated and the default settings don't get the best performance • the tools are not as good as commercial tools in terms of PPA. • intel would have done a lot of hand tuning and careful layout design to get the maximum PPA • Thomas Parry's analog design is for a 2GHz radio, so these frequencies are definitely possible.
@User @User thoughts?
j

Jecel Assumpção Jr

03/31/2022, 1:53 PM
It is not reasonable to expect to be able to throw some Verilog files into a simple tool and get in minutes the same result Intel's hundreds of engineers took years of hard work to achieve.
👍 4
Note that the bulk of any project is not very critical. You can use the automated tools for that (Intel does as well). By hand crafting the 10% that matters you can go from 100MH to 1GHz in the same process technology
a

Arman Avetisyan

03/31/2022, 6:16 PM
The sky130 hd is pretty slow. With the sky130 HS you barely get 3GHz in two flip flops chained. I would assume you need to blame the technology, which is a 150nm (not 130nm), the balance the stdcell libraries choose: area and power over speed. You should be able to get much better speeds with speed-targeted library. The current tools are pretty bad. They dont really optimize the synthesis result (as the RESIZER does pretty poor job for this) and at the end you get the result you get. I think using better tools + better PDK + some microarchitecture choices (like using multiple phase shifted clocks) you should be able to get 1GHz.
👍 1
🙏 1
j

Jecel Assumpção Jr

03/31/2022, 6:29 PM
All standard cell libraries I have seen have huge built-in margins so that the software that connects them together can do so safely with simple rules. A hand crafted circuit would individually size each transistor for high speed.
a

Arman Avetisyan

03/31/2022, 6:45 PM
"have huge built-in margins" all of the stdcells I saw use exact values, without any margins. I would assume sky130 stdcells are the same. However, the effect you are describing is achieved with different method, not just increasing/decreasing the delays of the library.
E.G. derates, parasitics overengineering, clock pessimism, other pessimisms, margins in the STA/Placer/Router/etc (not in the sky130 stdcells). SKY130 PDK has pretty bad characteristics for such huge technology. The worst case to best case scenario is over 100% delay/strength difference. In other tech nodes/PDKs the difference is 25-50%.
f

FatsieFS

04/01/2022, 4:04 PM
I want to add that having for high frequency designs you need long pipelines together with proper support in your design for branch prediction, out-of-order execution, etc.
e

Eric Smith

04/02/2022, 6:06 AM
@User Do you have a particular project that you're wondering about? To form an answer to the question one would have to compare the predicted speed to the measured speed first.