I was looking through documentation and various files to try to figure out what devices to use for an analog design, and I've accumulated a number of questions. Sorry if this is the wrong place. Someone told me to ask questions about the pdk in the efabless channel 1) It looks like the only high-voltage logic library is sky130_fd_sc_hvl, but the drawing for the g5v0d10v5 mosfets shows a Deep N-Well. Does the sky130_fd_sc_hvl have to be in a DNW? 2) Why are some devices and not others in the device list at https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html ? For instance, none of the rf_ fets are listed. 3) why are multiple devices missing from sky130_fd_pr.cdl, such as any pmos that isn't 1.8v ?

I make all my designs using Magic VLSI. This are the NMOS and PMOS devices available for layout generation using this tool. There is no need to use the DNW layer. At least, I don't use them and my designs still pass the MPW precheck.

@User: (1) I'm not sure where you see that the "drawing for the g5v0d10v5 mosfets shows a Deep N-Well". The deep n-well layer is always optional and can be placed under any FET transistors, 1.8V or 3.3V. The HVL logic is, by itself, not drawn in deep n-well. (2) RF FETs are not devices in the sense of having different models. They are just best-practice layouts for RF use of standard FETs. There have been plenty of lingering questions about whether there should be separate RF models, as well as questions about whether the RF layouts are really best-practice or not, but that's a separate issue. (3) We concentrated on making sure there is a complete set of SPICE subcircuits and models. The CDL is from what was in the original SkyWater sources, now in skywater-pdk. They appear to be mostly the subcircuits of the RF layouts. I am not aware of any of the open source tools that are using the CDL.

(1) https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html. In the section for "5.0V/10.5V NMOS FET", there is a cross-section that shows deep n-well. For comparison, the cross-section for "1.8V low-VT NMOS FET" does not show a deep n-well.

@User: I see. That should be logged on the github issue tracker for skywater-pdk. It's not wrong, but consistency isn't one of the strong points of this PDK.

Yeah, PNP diagram does not show a DNW, but NPN does, because it's obviously required for the NPN. I wasn't sure if there was a similar thing going on for the HV fets