@User The space available for inductors will probably be much the same on the redistribution layer and on any other metal layers, because inductors on other layers underneath redistribution layer metal such as a solderbump will not work due to magnetic effects - it would be basically a shorted turn. The redistribution layer and top metal layers could be used to make transformers, there is a balun made like that on a chip I did here (die photo at the end): http://www.chrisj.org/papers/ISSCC/ISSCC2007_19p1.pdf I would like to encourage you to please make it allowable for designers to selectively remove bumps and other redistribution layer metal that is not essential for the testing harness that is mandatory on all chips. i.e. provide a template of the redistribution layer layout that most people should use with all bumps present, and another template showing the minimum that is mandatory to keep, and let people keep or delete some redistribution metal as long as the mandatory parts are still there. This would be ideal for analog/RF stuff, because for things like LNAs, the inductors need to be in a specific location relative to the RF IO pads, and putting them in the middle may not be a usable option. I suspect that people would want RF IO pads near an edge of the chip to allow a good microstrip PCB trace to them. And thank you for all of the effort that you are putting into this, when I read back my posts they seem very greedy but really any access at all to this technology is a wonderful opportunity!

What prevents us from making circles or arcs

Mainly the lack of support for circles and arcs in the process design rules. The process rules indicate that you can use 45 degree angles on some layers, and that's about it. The redistribution layer might be more lenient about the allowed angles; I haven't looked at the RDL rules closely yet.